RTL Design Engineer

THE ROLE :

Serdes RTL team is looking for passionate and experienced Design Engineer for Digital/RTL Design of high speed Serdes IPs.  Be a part of the definition, design and development phase of industry leading and differentiating IPs for various industry protocols as well as proprietary PHYs such as EPYC's infinity data fabric.  This opportunity provides a balance of design definition, specification , ASIC digital logic design, debug, light exposure to embedded firmware along with timing closure. 

Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge and differentiating IPs.  

THE PERSON :

• Strong analytical/problem solving skills and pronounced attention to details.
• Must be a self starter, and able to independently drive tasks to completion.
• Strong interpersonal and communication skills

 RESPONSIBILITIES:

• Micro-architecture of digital blocks including hardware and firmware partitioning.
• Compile microarchitectural specs for unit level blocks and review with architects and senior designers.
• Digital design and RTL coding.
• Modifying or Writing firmware for embedded u-controllers in C with the help of Firmware engineers

PREFERRED SKILL SETS :

• Experience in digital design engineering e with successful tape-outs and technical leadership
• Serdes (Serializer/Deserializer) RTL and Design experience is a plus
• Excellent knowledge of Verilog HDL.
• Strong understanding of digital and analog electronics.
• Experience with low level, physical phenomena oriented logic design is an asset (dealing with IO, clocking, voltage control oscillators,  etc.)
• Good understanding of computer organization/architecture.
• Strong analytical/problem solving skills and pronounced attention to details.
• Must be a self starter, and able to independently drive tasks to completion.
• Strong interpersonal and communication skills

EDUCATION:

• Bachelor's degree in Electrical or Computer engineering is required. Master's or PhD degree is a plus.