GRAPHICS CORE IP DESIGN VERIFICATION STAFF ENGINEER

THE ROLE:

This opportunity is for a full-time, experienced engineer who has a passion for the digital design and verification of large-scale, complex computer hardware processors. The successful candidate will be working as part of the overall design verification (DV) team developing designs for AMD’s next generation Graphics IP (GFXIP). Our DV team focuses on functional and performance verification, as well as modelling, and develops components that are scalable and portable across different levels of DV.  We use state-of-the-art tools and methodologies and deliver into cutting-edge silicon technologies.  The successful candidate will work closely with various teams including design, architecture, and project management, to ensure the RTL delivery meets the specified requirements and schedule.

THE PERSON:

Besides a passion for modern, complex processor architecture, digital design, and verification in general, these personal qualities are essential for success in this role:

• Proven analytical skills
• Outstanding verbal and written communication
• A self-starter who excels at driving tasks to completion
• Enables collaboration within the team and thrives in resolving complex problems
• Enjoys working in a dynamic, fast-paced environment, engaging with multiple AMD sites globally
• Possesses a genuine desire for innovation

KEY RESPONSIBILITIES:

• Implement and deliver the Geometry Engine (GE) C-model for simulation (CSIM)
• Work closely with the Geometry DV team to achieve program metrics and deliverables
• Collaborate with the architecture and design teams across multiple parallel programs
• Understand the underlying architecture of the GE
• Identify dependencies, bottlenecks, and risks in the earlier phases of development
• Define practical effort estimates that translate to schedule impact statements
• Drive new improvements and initiatives across the broader team

REQUIREMENTS:

• Extensive experience in DV for ASIC development
• Fluent and experienced in coding C++ designs for ASIC development
• Graphics IP DV experience preferred
• Demonstrated analytical skills and attention to detail
• Understanding of hardware architecture
• Experience with System Verilog and UVM methodology
• Experience collaborating with modelling, methodology, and infrastructure teams
• Knowledge of IP/SoC level verification flows and methodologies
• Exposure to design and verification tools - VCS or equivalent simulator, debug tools such as Verdi and waveform viewers, and Synopsys VC Formal suite of DV applications
• Familiar with Linux programming and scripting, in Perl, TCL or similar

ACADEMIC CREDENTIALS:

• Bachelor’s (preferably Master’s) degree in Computer Engineering, Computer Science, Electrical Engineering or similar