About Job

CTC Undisclosed Job Location Canada Experience 3 - 6 yrs

Description

This person will be a member of the Chip Engineering Team, working on design and verification of state-of-the art InP-based photonic integrated circuits (PICs).

The successful candidate will contribute to the photomask layout design and, more specifically, development and adaptation of the related CAD tools.

Responsibilities:

G enerating and maintaining Photomask layout design Quality control of photomask design process Automation of photomask layout design process Communication and collaboration with internal groups and wafer fabrication foundries

Challenges:

The opportunity to work within a very flexible team and be involved in many facets of the PIC design and fabrication. The role offers the ability to be self directed within the wider objectives of the project, yet requires a capability to plan, perform and report on target. Organization, planning and attention to detail to ensure design meets layout rules, program schedules and project milestones.

Requirements:

BS or higher degree in related areas of engineering (e.g. Electrical Engineering) or science (e.g. Material Sciences) (Student)

KNOWLEDGE/SKILLS:

Extensive work experience with LEdit , DW2000, Cadence Excellent programming skills, proficiency in C/C , Python and MATLAB Familiar with semiconductor wafer fabrication methods (III-V, Silicon, MEMS) and device layout. Effective writing and communication skills to work with in house design group and external fabrication sites. EXPERIENCE:

At least 3 years of practical work in the area with proven record of achievement (sample photomask layout design / automotive design tools, etc.) required .