About Job

CTC Undisclosed Job Location Canada Experience 0 - 3 yrs

Description

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx, we care deeply about creating significant development experiences while building a strong sense of belonging and connection. We champion an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Xilinx is looking for a talented individual to join the Wired IP Solutions Group (WISG) in the position of Senior ASIC/FPGA Verification Engineer . The successful candidate will join our design Verification team developing ASIC and FPGA-based intellectual property (IP) to address the needs of state-of-the-art wired communications systems.

It is expected that the candidate will be experienced in SystemVerilog coding, and advanced verification methodologies such as constraint-random or UVM.. Working knowledge of RTL design and processes would be an asset, as would experience with scripting languages such as Python, Perl and TCL. It would also be desirable for applicants to have experience with wired communications protocols such as Ethernet, OTN and Interlaken.

Education Requirements

BSEE minimum required

Years of Experience

7 experience in ASIC/FPGA verification

Extensive experience in designing and implementing testbenches, coverage closure techniques and regression management flows

In depth knowledge of modern verification practices including UVM, Formal Verification and assertion based test

Experience and knowledge of communications standards (such as Ethernet, Flex Ethernet, OTN, Interlaken)

Fluency in Verilog or System Verilog

Excellent written and verbal communication skills

Desired:

Expertise in scripting languages such as Python, Perl and TCL

Experience in C, C

Familiarity with Xilinx tools and flows